Tổng Hợp POST Code Lỗi Trên Card Test Main Chi Tiết 2021

Là một kỷ thuật viên sửa máy tính thì không thể nào thiếu 1 chiếc Card Test Main, mà để xác định được chính xác lỗi thì bạn phải biết POST Code hiển thị trên Card Test có ý nghĩ gì. Vì vậy hôm nay mình viết bài viết tổng hợp này để mọi người có thể hiểu nó!

MỘT SỐ POST CODE THÔNG DỤNG:

POST CODE

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INTEL BIOS

D0 NMI is Disabled. Onboard KBC, RTC enabled (if present). Init code Checksum verification starting.
D1 Keyboard controller BAT test, CPU ID saved, and going to 4 GB flat mode.
D3 Do necessary chipset initialization, start memory refresh, and do memory sizing.
D4 Verify base memory.
D5 Init code to be copied to segment 0 and control to be transferred to segment 0.
D6 Control is in segment 0. To check recovery mode and verify main BIOS checksum. If either it is recovery mode or main BIOS checksum is bad, go to check point E0 for recovery else go to check point D7 for giving control to main BIOS.
D7 Find Main BIOS module in ROM image.
D8 Uncompress the main BIOS module.
D9 Copy main BIOS image to F000 shadow RAM and give control to main BIOS in F000 shadow RAM.
E0 Onboard Floppy Controller (if any) is initialized. Compressed recovery code is uncompressed in F000:0000 in Shadow RAM and give control to recovery code in F000 Shadow RAM. Initialize interrupt vector tables, initialize system timer, initialize DMA controller and interrupt controller.
E8 Initialize extra (Intel Recovery) Module.
E9 Initialize floppy drive.
EA Try to boot from floppy. If reading of boot sector is successful, give control to boot sector code.
EB Booting from floppy failed, look for ATAPI (LS-120, Zip) devices.
EC Try to boot from ATAPI. If reading of boot sector is successful, give control to boot sector code.
EF Booting from floppy and ATAPI device failed. Give two beeps. Retry the booting procedure again (go to check point E9).
03 NMI is Disabled. To check soft reset/power-on.
05 BIOS stack set. Going to disable cache if any.
06 POST code to be uncompressed.
07 CPU init and CPU data area init to be done.
08 CMOS checksum calculation to be done next.
0B Any initialization before keyboard BAT to be done next.
0C KB controller I/B free. To issue the BAT command to keyboard controller
0E Any initialization after KB controller BAT to be done next.
0F Keyboard command byte to be written.
10 Going to issue Pin-23,24 blocking/unblocking command.
11 Going to check pressing of <INS>, <END> key during power-on.
12 To init CMOS if “Init CMOS in every boot” is set or <END> key is pressed. Going to disable DMA and Interrupt controllers.
13 Video display is disabled and port-B is initialized. Chipset init about to begin.
14 8254 timer test about to start.
19 About to start memory refresh test.
1A Memory Refresh line is toggling. Going to check 15 µs ON/OFF time.
23 To read 8042 input port and disable Megakey GreenPC feature. Make BIOS code segment writeable.
24 To do any setup before Int vector init.
25 Interrupt vector initialization to begin. To clear password if necessary.
27 Any initialization before setting video mode to be done.
28 Going for monochrome mode and color mode setting.
2A Different buses init (system, static, output devices) to start if present. (See Section 4.3 for details of different buses.)
2B To give control for any setup required before optional video ROM check.
2C To look for optional video ROM and give control.
2D To give control to do any processing after video ROM returns control.
2E If EGA/VGA not found then do display memory R/W test.
2F EGA/VGA not found. Display memory R/W test about to begin.
30 Display memory R/W test passed. About to look for the retrace checking.
31 Display memory R/W test or retrace checking failed. To do alternate Display memory R/W test.
32 Alternate Display memory R/W test passed. To look for the alternate display retrace checking.
34 Video display checking over. Display mode to be set next.
37 Display mode set. Going to display the power-on message.
38 Different buses init (input, IPL, general devices) to start if present. (See Section 4.3 for details of different buses.)
39 Display different buses initialization error messages. (See Section 4.3 for details of different buses.)
3A New cursor position read and saved. To display the Hit <DEL> message.
40 To prepare the descriptor tables.
42 To enter in virtual mode for memory test.
43 To enable interrupts for diagnostics mode.
44 To initialize data to check memory wrap around at 0:0.
45 Data initialized. Going to check for memory wrap around at 0:0 and finding the total system memory size.
46 Memory wrap around test done. Memory size calculation over. About to go for writing patterns to test memory.
47 Pattern to be tested written in extended memory. Going to write patterns in base 640k memory.
48 Patterns written in base memory. Going to find out amount of memory below 1M memory.
49 Amount of memory below 1M found and verified. Going to find out amount of memory above 1M memory.
4B Amount of memory above 1M found and verified. Check for soft reset and going to clear memory below 1M for soft reset. (If power on, go to check point # 4Eh).
4C Memory below 1M cleared. (SOFT RESET) Going to clear memory above 1M.
4D Memory above 1M cleared. (SOFT RESET) Going to save the memory size. (Go to check point # 52h).
4E Memory test started. (NOT SOFT RESET) About to display the first 64k memory size.
4F Memory size display started. This will be updated during memory test. Going for sequential and random memory test.
50 Memory testing/initialization below 1M complete. Going to adjust displayed memory size for relocation/shadow.
51 Memory size display adjusted due to relocation/ shadow. Memory test above 1M to follow.
52 Memory testing/initialization above 1M complete. Going to save memory size information.
53 Memory size information is saved. CPU registers are saved. Going to enter in real mode.
54 Shutdown successful, CPU in real mode. Going to disable gate A20 line and disable parity/NMI.
57 A20 address line, parity/NMI disable successful. Going to adjust memory size depending on relocation/shadow.
58 Memory size adjusted for relocation/shadow. Going to clear Hit <DEL> message.
59 Hit <DEL> message cleared. <WAIT…> message displayed. About to start DMA and interrupt controller test.
60 DMA page register test passed. To do DMA#1 base register test.
62 DMA#1 base register test passed. To do DMA#2 base register test.
65 DMA#2 base register test passed. To program DMA unit 1 and 2.
66 DMA unit 1 and 2 programming over. To initialize 8259 interrupt controller.
7F Extended NMI sources enabling is in progress.
80 Keyboard test started. Clearing output buffer, checking for stuck key, to issue keyboard reset command.
81 Keyboard reset error/stuck key found. To issue keyboard controller interface test command.
82 Keyboard controller interface test over. To write command byte and init circular buffer.
83 Command byte written, global data init done. To check for lock-key.
84 Lock-key checking over. To check for memory size mismatch with CMOS.
85 Memory size check done. To display soft error and check for password or bypass setup.
86 Password checked. About to do programming before setup.
87 Programming before setup complete. To uncompress SETUP code and execute CMOS setup.
88 Returned from CMOS setup program and screen is cleared. About to do programming after setup.
89 Programming after setup complete. Going to display power-on screen message.
8B First screen message displayed. <WAIT…> message displayed. PS/2 Mouse check and extended BIOS data area allocation to be done.
8C Setup options programming after CMOS setup about to start.
8D Going for hard disk controller reset.
8F Hard disk controller reset done. Floppy setup to be done next.
91 Floppy setup complete. Hard disk setup to be done next.
95 Init of different buses optional ROMs from C800 to start. (See Section 4.3 for details of different buses.)
96 Going to do any init before C800 optional ROM control.
97 Any init before C800 optional ROM control is over. Optional ROM check and control will be done next.
98 Optional ROM control is done. About to give control to do any required processing after optional ROM returns control and enable external cache.
99 Any initialization required after optional ROM test over. Going to setup timer data area and printer base address.
9A Return after setting timer and printer base address. Going to set the RS-232 base address.
9B Returned after RS-232 base address. Going to do any initialization before Coprocessor test.
9C Required initialization before Coprocessor is over. Going to initialize the Coprocessor next.
9D Coprocessor initialized. Going to do any initialization after Coprocessor test.
9E Initialization after Coprocessor test is complete. Going to check extended keyboard, keyboard ID and num-lock.
A2 Going to display any soft errors.
A3 Soft error display complete. Going to set keyboard typematic rate.
A4 Keyboard typematic rate set. To program memory wait states.
A5 Going to enable parity/NMI.
A7 NMI and parity enabled. Going to do any initialization required before giving control to optional ROM at E000.
A8 Initialization before E000 ROM control over. E000 ROM to get control next.
A9 Returned from E000 ROM control. Going to do any initialization required after E000 optional ROM control.
AA Initialization after E000 optional ROM control is over. Going to display the system configuration.
AB Put INT13 module runtime image to shadow.
AC Generate MP for multiprocessor support (if present).
AD Put CGA INT10 module (if present) in Shadow.
AE Uncompress SMBIOS module and init SMBIOS code and form the runtime SMBIOS image in shadow.
B1 Going to copy any code to specific area.
00 Copying of code to specific area done. Going to give control to INT-19 boot loader.

AMI BIOS

00 – Code copying to specific areas is done. Passing control to INT 19h boot loader next.
03 – The NMI is disabled. Next, checking for a soft reset or a power on condition.
05 – The BIOS stack has been built. Next, disabling cache memory.
06 – Uncompressing the POST code next.
07 – Next, initializing the CPU and the CPU data area.
08 – The CMOS checksum calculation is done next.
0A – The CMOS checksum calculation is done. Initializing the CMOS status register for date and time next.
0B – The CMOS status register is initialized. Next, performing any required initialization before the keyboard BAT command is issued.
0C – The keyboard controller input buffer is free. Next, issuing the BAT command to the keyboard controller.
0E – The keyboard controller BAT command result has been verified. Next, performing any necessary initialization after the keyboard controller BAT command test.
0F – The initialization after the keyboard controller BAT command test is done. The keyboard command byte is written next.
10 – The keyboard controller command byte is written. Next, issuing the Pin 23 and 24 blocking and unblocking command.
11 – Next, checking if <End> or <Ins> keys were pressed during power on. Initializing CMOS RAM if the Initialize CMOS RAM in every boot AMIBIOS POST option was set in AMIBCP or the <End> key was pressed.
12 – Next, disabling DMA controllers 1 and 2 and interrupt controllers 1 and 2.
13 – The video display has been disabled. Port B has been initialized. Next, initializing the chipset.
14 – The 8254 timer test will begin next.
19 – The 8254 timer test is over. Starting the memory refresh test next.
1A – The memory refresh line is toggling. Checking the 15 second on/off time next.
23 – Reading the 8042 input port and disabling the MEGAKEY Green PC feature next. Making the BIOS code segment writable and performing any necessary configuration before initializing the interrupt vectors.
24 – The configuration required before interrupt vector initialization has completed. Interrupt vector initialization is about to begin.
25 – Interrupt vector initialization is done. Clearing the password if the POST DIAG switch is on.
27 – Any initialization before setting video mode will be done next.
28 – Initialization before setting the video mode is complete. Configuring the monochrome mode and color mode settings next.
2A – Initializing the different bus system, static, and output devices, if present.
2B – Passing control to the video ROM to perform any required configuration before the video ROM test.
2C – All necessary processing before passing control to the video ROM is done. Looking for the video ROM next and passing control to it.
2D – The video ROM has returned control to BIOS POST. Performing any required processing after the video ROM had control.
2E – Completed post-video ROM test processing. If the EGA/VGA controller is not found, performing the display memory read/write test next.
2F – The EGA/VGA controller was not found. The display memory read/write test is about to begin.
30 – The display memory read/write test passed. Look for retrace checking next.
31 – The display memory read/write test or retrace checking failed. Performing the alternate display memory read/write test next.
32 – The alternate display memory read/write test passed. Looking for alternate display retrace checking next.
34 – Video display checking is over. Setting the display mode next.
37 – The display mode is set. Displaying the power on message next.
38 – Initializing the bus input, IPL, general devices next, if present.
39 – Displaying bus initialization error messages.
3A – The new cursor position has been read and saved. Displaying the Hit <DEL> message next.
3B – The Hit <DEL> message is displayed. The protected mode memory test is about to start.
40 – Preparing the descriptor tables next.
42 – The descriptor tables are prepared. Entering protected mode for the memory test next.
43 – Entered protected mode. Enabling interrupts for diagnostics mode next.
44 – Interrupts enabled if the diagnostics switch is on. Initializing data to check memory wraparound at 0:0 next.
45 – Data initialized. Checking for memory wraparound at 0:0 and finding the total system memory size next.
46 – The memory wraparound test is done. Memory size calculation has been done. Writing patterns to test memory next.
47 – The memory pattern has been written to extended memory. Writing patterns to the base 640 KB memory next.
48 – Patterns written in base memory. Determining the amount of memory below 1 MB next.
49 – The amount of memory below 1 MB has been found and verified. Determining the amount of memory above 1 MB memory next.
4B – The amount of memory above 1 MB has been found and verified. Checking for a soft reset and clearing the memory below 1 MB for the soft reset next. If this is a power on situation, going to checkpoint 4Eh next.
4C – The memory below 1 MB has been cleared via a soft reset. Clearing the memory above 1 MB next.
4D – The memory above 1 MB has been cleared via a soft reset. Saving the memory size next. Going to checkpoint 52h next.
4E – The memory test started, but not as the result of a soft reset. Displaying the first 64 KB memory size next.
4F – The memory size display has started. The display is updated during the memory test. Performing the sequential and random memory test next.
50 – The memory below 1 MB has been tested and initialized. Adjusting the displayed memory size for relocation and shadowing next.
51 – The memory size display was adjusted for relocation and shadowing. Testing the memory above 1 MB next.
52 – The memory above 1 MB has been tested and initialized. Saving the memory size information next.
53 – The memory size information and the CPU registers are saved. Entering real mode next.
54 – Shutdown was successful. The CPU is in real mode. Disabling the Gate A20 line, parity, and the NMI next.
57 – The A20 address line, parity, and the NMI are disabled. Adjusting the memory size depending on relocation and shadowing next.
58 – The memory size was adjusted for relocation and shadowing. Clearing the Hit <DEL> message next.
59 – The Hit <DEL> message is cleared. The <WAIT…> message is displayed. Starting the DMA and interrupt controller test next.
60 – The DMA page register test passed. Performing the DMA Controller 1 base register test next.
62 – The DMA controller 1 base register test passed. Performing the DMA controller 2 base register test next.
65 – The DMA controller 2 base register test passed. Programming DMA controllers 1 and 2 next.
66 – Completed programming DMA controllers 1 and 2. Initializing the 8259 interrupt controller next.
67 – Completed 8259 interrupt controller initialization.
7F – Extended NMI source enabling is in progress.
80 – The keyboard test has started. Clearing the output buffer and checking for stuck keys. Issuing the keyboard reset command next.
81 – A keyboard reset error or stuck key was found. Issuing the keyboard controller interface test command next.
82 – The keyboard controller interface test completed. Writing the command byte and initializing the circular buffer next.
83 – The command byte was written and global data initialization has completed. Checking for a locked key next.
84 – Locked key checking is over. Checking for a memory size mismatch with CMOS RAM data next.
85 – The memory size check is done. Displaying a soft error and checking for a password or bypassing WINBIOS Setup next.
86 – The password was checked. Performing any required programming before WINBIOS Setup next.
87 – The programming before WINBIOS Setup has completed. Uncompressing the WINBIOS Setup code and executing the AMIBIOS Setup or WINBIOS Setup utility next.
88 – Returned from WINBIOS Setup and cleared the screen. Performing any necessary programming after WINBIOS Setup next.
89 – The programming after WINBIOS Setup has completed. Displaying the power on screen message next.
8B – The first screen message has been displayed. The <WAIT…> message is displayed. Performing the PS/2 mouse check and extended BIOS data area allocation check next.
8C – Programming the WINBIOS Setup options next.
8D – The WINBIOS Setup options are programmed. Resetting the hard disk controller next.
8F – The hard disk controller has been reset. Configuring the floppy drive controller next.
91 – The floppy drive controller has been configured. Configuring the hard disk drive controller next.
95 – Initializing bus adaptor ROMs from C8000h through D8000h.
96 – Initializing before passing control to the adaptor ROM at C800.
97 – Initialization before the C800 adaptor ROM gains control has completed. The adaptor ROM check is next.
98 – The adaptor ROM had control and has now returned control to BIOS POST. Performing any required processing after the option ROM returned control.
99 – Any initialization required after the option ROM test has completed. Configuring the timer data area and printer base address next.
9A – Set the timer and printer base addresses. Setting the RS-232 base address next.
9B – Returned after setting the RS-232 base address. Performing any required initialization before the Coprocessor test next.
9C – Required initialization before the Coprocessor test is over. Initializing the Coprocessor next.
9D – Coprocessor initialized. Performing any required initialization after the Coprocessor test next.
9E – Initialization after the Coprocessor test is complete. Checking the extended keyboard, keyboard ID, and Num Lock key next. Issuing the keyboard ID command next.
A2 – Displaying any soft errors next.
A3 – The soft error display has completed. Setting the keyboard typematic rate next.
A4 – The keyboard typematic rate is set. Programming the memory wait states next.
A5 – Memory wait state programming is over. Clearing the screen and enabling parity and the NMI next.
A7 – NMI and parity enabled. Performing any initialization required before passing control to the adaptor ROM at E000 next.
A8 – Initialization before passing control to the adaptor ROM at E000h completed. Passing control to the adaptor ROM at E000h next.
A9 – Returned from adaptor ROM at E000h control. Performing any initialization required after the E000 option ROM had control next.
AA – Initialization after E000 option ROM control has completed. Displaying the system configuration next.
AB – Uncompressing the DMI data and executing DMI POST initialization next.
B0 – The system configuration is displayed.
B1 – Copying any code to specific areas.
D0 – The NMI is disabled. Power on delay is starting. Next, the initialization code checksum will be verified.
D1 – Initializing the DMA controller, performing the keyboard controller BAT test, starting memory refresh, and entering 4 GB flat mode next.
D3 – Starting memory sizing next.
D4 – Returning to real mode. Executing any OEM patches and setting the stack next.
D5 – Passing control to the uncompressed code in shadow RAM at E000:0000h. The initialization code is copied to segment 0 and control will be transferred to segment 0.
D6 – Control is in segment 0. Next, checking if <Ctrl> <Home> was pressed and verifying the system BIOS checksum. If either <Ctrl> <Home> was pressed or the system BIOS checksum is bad, next will go to checkpoint code E0h. Otherwise, going to checkpoint code D7h.
E0 – The onboard floppy controller if available is initialized. Next, beginning the base 512 KB memory test.
E1 – Initializing the interrupt vector table next.
E2 – Initializing the DMA and Interrupt controllers next.
E6 – Enabling the floppy drive controller and Timer IRQs. Enabling internal cache memory.
ED – Initializing the floppy drive.
EE – Looking for a floppy diskette in drive A:. Reading the first sector of the diskette.
EF – A read error occurred while reading the floppy drive in drive A:.
F0 – Next, searching for the AMIBOOT.ROM file in the root directory.
F1 – The AMIBOOT.ROM file is not in the root directory.
F2 – Next, reading and analyzing the floppy diskette FAT to find the clusters occupied by the AMIBOOT.ROM file.
F3 – Next, reading the AMIBOOT.ROM file, cluster by cluster.
F4 – The AMIBOOT.ROM file is not the correct size.
F5 – Next, disabling internal cache memory.
FB – Next, detecting the type of flash ROM.
FC – Next, erasing the flash ROM.
FD – Next, programming the flash ROM.
FF – Flash ROM programming was successful. Next, restarting the system BIOS.

Award BIOS

01 – Expand the Xgroup codes located in physical memory address 1000:0
03 – Initial Superio_Early_Init switch
05 – Blank out screen; Clear CMOS error flag
07 – Clear 8042 interface; Initialize 8042 self test
08 – Test special keyboard controller for Winbond 977 series Super I/O chips; Enable keyboard interface
0A – Disable PS/2 mouse interface (optional); Auto detect ports for keyboard & mouse followed by a port & interface swap (optional); Reset keyboard for Winbond 977 series Super I/O chips
0E – Test F000h segment shadow to see whether it is read/write capable or not. If test fails, keep beeping the speaker
10 – Auto detect flash type to load appropriate flash read/write codes into the run time area in F000 for ESCD & DMI support
12 – Use walking 1’s algorithm to check out interface in CMOS circuitry. Also set real time clock power status and then check for overrride
14 – Program chipset default values into chipset. Chipset default values are MODBINable by OEM customers
16 – Initial Early_Init_Onboard_Generator switch
18 – Detect CPU information including brand, SMI type (Cyrix or Intel) and CPU level (586 or 686)
1B – Initial interrupts vector table. If no special specified, all H/W interrupts are directed to SPURIOUS_INT_HDLR & S/W interrupts to SPURIOUS_soft_HDLR
1D – Initial EARLY_PM_INIT switch
1F – Load keyboard matrix (notebook platform)
21 – HPM initialization (notebook platform)
23 – Check validity of RTC value; Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead; Prepare BIOS resource map for PCI & PnP use. If ESCD is valid, take into consideration of the ESCD’s legacy information; Onboard clock generator initialization. Disable respective clock resource to empty PCI & DIMM slots; Early PCI initialization – Enumerate PCI bus number, assign memory & I/O resource, search for a valid VGA device & VGA BIOS, and put it into C000:0
27 – Initialize INT 09 buffer
29 – Program CPU internal MTRR (P6 & PII) for 0-640K memory address; Initialize the APIC for Pentium class CPU; Program early chipset according to CMOS setup; Measure CPU speed; Invoke video BIOS
2D – Initialize multilanguage; Put information on screen display, including Award title, CPU type, CPU speed, etc…
33 – Reset keyboard except Winbond 977 series Super I/O chips
3C – Test 8254
3E – Test 8259 interrupt mask bits for channel 1
40 – Test 9259 interrupt mask bits for channel 2
43 – Test 8259 functionality
47 – Initialize EISA slot
49 – Calculate total memory by testing the last double last word of each 64K page; Program writes allocation for AMD K5 CPU
4E – Program MTRR of M1 CPU; initialize L2 cache for P6 class CPU & program cacheable range; Initialize the APIC for P6 class CPU; On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical
50 – Initialize USB
52 – Test all memory (clear all extended memory to 0)
55 – Display number of processors (multi-processor platform)
57 – Display PnP logo; Early ISA PnP initialization and assign CSN to every ISA PnP device
59 – Initialize the combined Trend Anti-Virus code
5B – Show message for entering AWDFLASH.EXE from FDD (optional feature)
5D – Initialize Init_Onboard_Super_IO switch; Initialize Init_Onboard_AUDIO switch
60 – Okay to enter Setup utility
65 – Initialize PS/2 mouse
67 – Prepare memory size information for function call: INT 15h ax=E820h
69 – Turn on L2 cache
6B – Program chipset registers according to items described in Setup & Auto-Configuration table
6D – Assign resources to all ISA PnP devices; Auto assign ports to onboard COM ports if the corresponding item in Setup is set to ‘AUTO’
6F – Initialize floppy controller; Setup floppy related fields in 40:hardware
73 – Enter AWDFLASH.EXE if: AWDFLASH.EXE is found in floppy dive and ALT+F2 is pressed
75 – Detect and install all IDE devices: HDD, LS120, ZIP, CDROM…
77 – Detect serial ports and parallel ports
7A – Detect and install coprocessor
7F – Switch back to text mode if full screen logo is supported: if errors occur, report errors & wait for keys, if no errors occur or F1 key is pressed continue – Clear EPA or customization logo
82 – Call chipset power management hook: Recover the text fond used by EPA logo (not for full screen logo), If password is set, ask for password
83 – Save all data in stack back to CMOS
84 – Initialize ISA PnP boot devices
85 – Final USB initialization; NET PC: Build SYSID structure; Switch screen back to text mode; Set up ACPI table at top of memory; Invoke ISA adapter ROM’s; Assign IRQ’s to PCI devices; Initialize APM; Clear noise of IRQ’s
93 – Read HDD boot sector information for Trend Anti-Virus code
94 – Enable L2 cache; Program boot up speed; Chipset final initialization; Power management final initialization; Clear screen and display summary table; Program K^ write allocation; Program P6 class write combining
95 – Program daylight saving; Update keyboard LED and typematic rate
96 – Build MP table; Build and update ESCD; Set CMOS century to 20h or 19h; Load CMOS time into DOS timer tick; Build MSIRQ routing table
C0 – Early chipset initialization: Disable shadow RAM, L2 cache (socket 7 and below), program basic chipset registers
C1 – Detect memory: Auto detection of DRAM size, type and ECC, auto detection of L2 cache (socket 7 and below)
C3 – Expand compressed BIOS code to DRAM
C5 – Call chipset hook to copy BIOS back to E000 & F000 shadow RAM
CF – Test CMOS read/write functionality
FF – Boot attempt (INT 19h)

Phoenix BIOS

02 – Verify Real Mode
03 – Disable Non-Maskable Interrupt (NMI)
04 – Get CPU type
06 – Initialize system hardware
07 – Disable shadow and execute code from the ROM.
08 – Initialize chipset with initial POST values
09 – Set IN POST flag
0A – Initialize CPU registers
0B – Enable CPU cache
0C – Initialize caches to initial POST values
0E – Initialize I/O component
0F – Initialize the local bus IDE
10 – Initialize Power Management
11 – Load alternate registers with initial POST values
12 – Restore CPU control word during warm boot
13 – Initialize PCI Bus Mastering devices
14 – Initialize keyboard controller
16 – BIOS ROM checksum
17 – Initialize cache before memory Auto size
18 – 8254 timer initialization
1A – 8237 DMA controller initialization
1C – Reset Programmable Interrupt Controller
20 – Test DRAM refresh
22 – Test 8742 Keyboard Controller
24 – Set ES segment register to 4 GB
28 – Auto size DRAM
29 – Initialize POST Memory Manager
2A – Clear 512 kB base RAM
2C – RAM failure on address line xxxx*
2E – RAM failure on data bits xxxx* of low byte of memory bus
2F – Enable cache before system BIOS shadow
32 – Test CPU bus-clock frequency
33 – Initialize Phoenix Dispatch Manager
36 – Warm start shut down
38 – Shadow system BIOS ROM
3A – Auto size cache
3C – Advanced configuration of chipset registers
3D – Load alternate registers with CMOS values
41 – Initialize extended memory for RomPilot
42 – Initialize interrupt vectors
45 – POST device initialization
46 – Check ROM copyright notice
47 – Initialize I20 support
48 – Check video configuration against CMOS
49 – Initialize PCI bus and devices
4A – Initialize all video adapters in system
4B – QuietBoot start (optional)
4C – Shadow video BIOS ROM
4E – Display BIOS copyright notice
4F – Initialize MultiBoot
50 – Display CPU type and speed
51 – Initialize EISA board
52 – Test keyboard
54 – Set key click if enabled
55 – Enable USB devices
58 – Test for unexpected interrupts
59 – Initialize POST display service
5A – Display prompt ‘Press F2 to enter SETUP’
5B – Disable CPU cache
5C – Test RAM between 512 and 640 kB
60 – Test extended memory
62 – Test extended memory address lines
64 – Jump to UserPatch1
66 – Configure advanced cache registers
67 – Initialize Multi Processor APIC
68 – Enable external and CPU caches
69 – Setup System Management Mode (SMM) area
6A – Display external L2 cache size
6B – Load custom defaults (optional)
6C – Display shadow-area message
6E – Display possible high address for UMB recovery
70 – Display error messages
72 – Check for configuration errors
76 – Check for keyboard errors
7C – Set up hardware interrupt vectors
7D – Initialize Intelligent System Monitoring
7E – Initialize coprocessor if present
80 – Disable onboard Super I/O ports and IRQs
81 – Late POST device initialization
82 – Detect and install external RS232 ports
83 – Configure non-MCD IDE controllers
84 – Detect and install external parallel ports
85 – Initialize PC-compatible PnP ISA devices
86 – Re-initialize onboard I/O ports.
87 – Configure Motherboard Configurable Devices (optional)
88 – Initialize BIOS Data Area
89 – Enable Non-Maskable Interrupts (NMIs)
8A – Initialize Extended BIOS Data Area
8B – Test and initialize PS/2 mouse
8C – Initialize floppy controller
8F – Determine number of ATA drives (optional)
90 – Initialize hard-disk controllers
91 – Initialize local-bus hard-disk controllers
92 – Jump to UserPatch2
93 – Build MPTABLE for multi-processor boards
95 – Install CD ROM for boot
96 – Clear huge ES segment register
97 – Fix up Multi Processor table
98 – Search for option ROMs. One long, two short beeps on checksum failure
99 – Check for
SMART Drive
(optional)
9A – Shadow option ROMs
9C – Set up Power Management
9D – Initialize security engine (optional)
9E – Enable hardware interrupts
9F – Determine number of ATA and SCSI drives
A0 – Set time of day
A2 – Check key lock
A4 – Initialize typematic rate
A8 – Erase F2 prompt
AA – Scan for F2 key stroke
AC – Enter SETUP
AE – Clear Boot flag
B0 – Check for errors
B1 – Inform RomPilot about the end of POST.
B2 – POST done – prepare to boot operating system
B4 – 1 One short beep before boot
B5 – Terminate QuietBoot (optional)
B6 – Check password (optional)
B7 – Initialize ACPI BIOS
B9 – Prepare Boot
BA – Initialize SMBIOS
BB – Initialize PnP Option ROMs
BC – Clear parity checkers
BD – Display MultiBoot menu
BE – Clear screen (optional)
BF – Check virus and backup reminders
C0 – Try to boot with INT 19
C1 – Initialize POST Error Manager (PEM)
C2 – Initialize error logging
C3 – Initialize error display function
C4 – Initialize system error handler
C5 – PnPnd dual CMOS (optional)
C6 – Initialize note dock (optional)
C7 – Initialize note dock late
C8 – Force check (optional)
C9 – Extended checksum (optional)
CA – Redirect Int 15h to enable remote keyboard
CB – Redirect Int 13h to Memory Technologies Devices such as ROM, RAM, PCMCIA, and serial disk
CC – Redirect Int 10h to enable remote serial video
CD – Re-map I/O and memory for PCMCIA
CE – Initialize digitizer and display message
D2 – Unknown interrupt
E0 – Initialize the chipset
E1 – Initialize the bridge
E2 – Initialize the CPU
E3 – Initialize system timer
E4 – Initialize system I/O
E5 – Check force recovery boot
E6 – Checksum BIOS ROM
E7 – Go to BIOS
E8 – Set Huge Segment
E9 – Initialize Multi Processor
EA – Initialize OEM special code
EB – Initialize PIC and DMA
EC – Initialize Memory type
ED – Initialize Memory size
EE – Shadow Boot Block
EF – System memory test
F0 – Initialize interrupt vectors
F1 – Initialize Run Time Clock
F2 – Initialize video
F3 – Initialize System Management Manager
F4 – Output one beep
F5 – Clear Huge Segment
F6 – Boot to Mini DOS
F7 – Boot to Full DOS

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